A self-biased PLL with fixed ratio of bandwidth to input frequency was designed in paper. The self-biased PLL had the little influence of the process, temperature and voltage. VCO was optimized to reduce the jitter. The PLL operated in the frequency range from 500MHZ to 3125MHZ with 1.2V power supply in SMIC 65nm CMOS process. Simulation results showed the PLL had a peak-to-peak jitter of 8.7ps at 1.875GHZ output frequency with 32 mW of power.