In the proposed paper, a mixed number representation is being used in order to develop a low power, high speed multiplication algorithm. The redundant binary (RB) adder and booth decoder along with sign magnitude notation of the multiplicand, helps in achieving the reduced switching activity and low power dissipation. The high speed operation is achieved by accumulation of partial products (PP) through carry propagation free (CPF) using RB notation. Due to this, the switching activity during the PP generation process can be reduced on an average by 90%.The design proposed in paper dissipates much less power comparatively and is 18% faster on an average.