Vol. 2, Issue 5 (2015)
New efficient redundant radix 4 multiplier design using VHDL
Author(s): Jageshwar Prasad Sinha, Anil Kumar sahu
Abstract: With the growth of VLSI processing in the industrial sector the design of efficient algorithms for designing compact functional circuits has led to a competition among various industries.Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Some are more suitable for FPGA use than others. In the area of designing fast parallel algorithms for multiplying numbers, proposed algorithm for multiplying two n-bit signed binary numbers needs Ã© 2.71 log2nÃ¹ + 3 steps of single bit addition on an n Â´ n systolic architecture which outperforms the then best VLSI implementable algorithm with O(n) time and O(n2 ) hardware. The subsequent algorithms proposed by him for multiplying numbers in ternary and redundant-radix-four (RR-4) representations require still less time with 2 Ã©log2n Ã¹ + 2 and Ã©(1/2) log2n +1Ã¹ steps of single digit addition, respectively. Here we have proposed a novel approach for the multiplication of two numbers in RR4 number system. The results has been evaluated in ISE environment and the performance giving satisfactory results.